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Films / The memory towers behind the AI boom

  • AI
  • Chips

The memory towers behind the AI boom

Published 5 Nov 2026 · Last fact-checked 20 Oct 2026 · 16:03 · 23 claims, 28 sources

On this page

  1. In two sentences
  2. Chapters
  3. What we know
  4. Sources
  5. What you are seeing
  6. Transcript
  7. How it was made
  8. Corrections
  1. Summary
  2. Chapters
  3. What we know
  4. Sources
  5. What you see
  6. Transcript
  7. How it was made
  8. Corrections

In two sentences

Beside the fastest AI processors sit towers of stacked memory. This film opens one package to show why memory bandwidth matters, how the towers are built, tested and cooled, who makes them, and why their supply is reserved years before the computers exist.

Chapters

What we know and what we don'tWhat we know

Established

  • HBM is vertically stacked DRAM connected through a very wide interface and placed in the same package as a host accelerator.

    Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix partnership with TSMC (opens the source) ↗ · AMD: AMD launches first commercial HBM GPU family (opens the source) ↗ · SK hynix: SK hynix HBM development history (opens the source) ↗

  • NVIDIA specifies up to 288 GB of HBM4 per Rubin GPU; current official pages list either 19.2 or up to 22 TB/s of bandwidth depending on the page/configuration.

    NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗

  • Without speculative decoding, token-by-token LLM decode is commonly memory-bandwidth-bound, while prompt prefill commonly produces larger compute-bound matrix operations.

    NVIDIA Developer: Co-Designing AI Model Attention for Fast, Interactive Long-Context Inference (opens the source) ↗

Uncertain or limited

  • First, yield, performance, efficiency, and thermal comparisons are company claims.

    Samsung Electronics, Samsung commercial HBM4 shipments (opens the source) ↗

  • Agreement does not mean TSMC makes SK hynix DRAM core dies or that every HBM supplier uses the same structure.

    SK hynix, SK hynix partnership with TSMC (opens the source) ↗

  • AMD's 2015 comparative marketing does not describe current HBM4 or AI performance.

    AMD, AMD launches first commercial HBM GPU family (opens the source) ↗

  • A workload can be limited by compute throughput or memory bandwidth depending on how much arithmetic it performs per byte moved.

    Lawrence Berkeley National Laboratory: Roofline performance model (opens the source) ↗

  • HBM4 doubles the cited per-stack data interface from 1,024 to 2,048 I/Os relative to HBM3E.

    NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗

  • Samsung began HBM4 mass production and commercial shipment in February 2026, offering 12-layer 24-36 GB products and reporting up to 3.3 TB/s per stack.

    as the company reports

    Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗

  • HBM existed before the generative-AI boom; AMD commercialized the first HBM-powered GPU family in 2015 after development with SK hynix.

    AMD: AMD launches first commercial HBM GPU family (opens the source) ↗ · SK hynix: SK hynix HBM development history (opens the source) ↗

  • TSMC CoWoS integrates logic SoCs and HBM stacks, making advanced packaging part of accelerator capability rather than a cosmetic final step.

    TSMC: TSMC 2025 Annual Report (opens the source) ↗

  • HBM4 makes compute-memory co-design more important by using advanced logic base dies and a wider interface.

    NVIDIA Developer: Co-Designing AI Model Attention for Fast, Interactive Long-Context Inference (opens the source) ↗ · NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix partnership with TSMC (opens the source) ↗

  • SK hynix uses TSMC advanced logic for its HBM4 base die and collaborates with TSMC on CoWoS integration.

    SK hynix: SK hynix partnership with TSMC (opens the source) ↗

  • Stacking multiple TSV-connected dies creates distinct yield, test, and reliability challenges.

    IEEE Transactions on VLSI Systems: TSV built-in self-repair for HBM yield and reliability (opens the source) ↗ · SK hynix: SK hynix TSV wafer-level packaging process (opens the source) ↗ · Advantest: Advantest HBM test-flow briefing (opens the source) ↗ · Semiconductor Engineering: Current HBM known-good-stack test flows (opens the source) ↗

  • HBM manufacturing relies on screening before stacking and repeated testing after stacking because assembly can introduce connection, stress, and yield failures even when constituent dies passed earlier tests.

    IEEE Transactions on VLSI Systems: TSV built-in self-repair for HBM yield and reliability (opens the source) ↗ · SK hynix: SK hynix TSV wafer-level packaging process (opens the source) ↗ · Advantest: Advantest HBM test-flow briefing (opens the source) ↗ · Semiconductor Engineering: Current HBM known-good-stack test flows (opens the source) ↗

  • Higher stack density and faster interfaces make heat removal and thermal resistance important HBM design constraints.

    SK hynix: SK hynix MR-MUF heat-control history (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗

  • Future HBM stacks may use hybrid bonding to connect copper more directly and reduce space and resistance associated with micro-bumps, but adoption is not yet universal.

    SK hynix: SK hynix hybrid-bonding technical note (opens the source) ↗

  • SK hynix, Samsung, and Micron are the three major established HBM suppliers at the 2026 checkpoint.

    TrendForce: HBM Industry Analysis, Q2 2026 (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix Q2 2026 results (opens the source) ↗ · Micron: Micron HBM4 high-volume production announcement (opens the source) ↗ · Micron: Micron fiscal Q3 2026 prepared remarks (opens the source) ↗ · Micron: Micron fiscal Q1 2026 presentation (opens the source) ↗

  • SK hynix began mass shipments of HBM4 in Q2 2026 and planned to ramp production in H2.

    as the company reports

    SK hynix: SK hynix Q2 2026 results (opens the source) ↗

  • Micron reported HBM4 volume shipments beginning in Q1 2026 and more than $1 billion in HBM4 revenue shipped by fiscal Q3 2026.

    as the company reports

    Micron: Micron HBM4 high-volume production announcement (opens the source) ↗ · Micron: Micron fiscal Q3 2026 prepared remarks (opens the source) ↗

  • Samsung expected memory supply constraints to continue in H2 2026 despite production increases.

    Samsung Electronics: Samsung Q2 2026 results (opens the source) ↗

  • New HBM/advanced-packaging capacity takes years to construct; SK hynix's 2026 Indiana groundbreaking targets mass production in H2 2029.

    US National Institute of Standards and Technology: Current NIST CHIPS award listing for SK hynix Indiana (opens the source) ↗ · SK hynix: SK hynix Indiana groundbreaking (opens the source) ↗

  • The United States is supporting domestic HBM advanced-packaging capacity through the SK hynix Indiana project.

    US Department of Commerce: US CHIPS award for SK hynix HBM packaging (opens the source) ↗ · US National Institute of Standards and Technology: Current NIST CHIPS award listing for SK hynix Indiana (opens the source) ↗ · SK hynix: SK hynix Indiana groundbreaking (opens the source) ↗

  • Advanced HBM is strategically controlled by the United States because it is a key component of advanced AI and supercomputing systems.

    US Bureau of Industry and Security / Federal Register: US advanced HBM export controls (opens the source) ↗ · US Bureau of Industry and Security: Current BIS License Exception HBM rule (opens the source) ↗

  • Software can materially reduce HBM traffic; FlashAttention reorganizes exact attention to reduce reads/writes between HBM and on-chip SRAM.

    NeurIPS: FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness (opens the source) ↗

  • Company history.

    SK hynix, SK hynix HBM development history (opens the source) ↗

  • Official NVIDIA pages do not currently show one uniform bandwidth figure. These are vendor specifications, not measured application throughput.

    NVIDIA, NVIDIA Rubin architecture and current specification pages (opens the source) ↗

  • The model is an analytical framework; it does not prove that a particular AI workload is memory-bound without workload/platform inputs.

    Lawrence Berkeley National Laboratory, Roofline performance model (opens the source) ↗

  • NVIDIA platform/model analysis.

    NVIDIA Developer, Co-Designing AI Model Attention for Fast, Interactive Long-Context Inference (opens the source) ↗

  • Does not establish that all CoWoS capacity serves HBM, NVIDIA, or one product.

    TSMC, TSMC 2025 Annual Report (opens the source) ↗

  • Supports mechanism, not one current vendor's production yield or defect rate.

    IEEE Transactions on VLSI Systems, TSV built-in self-repair for HBM yield and reliability (opens the source) ↗

  • An educational description of SK hynix-related packaging methods, not one mandatory sequence for every supplier, HBM generation, or bonding flow.

    SK hynix, SK hynix TSV wafer-level packaging process (opens the source) ↗

  • Test-equipment supplier material. It establishes categories and insertion points, not a universal vendor recipe or current supplier yield.

    Advantest, Advantest HBM test-flow briefing (opens the source) ↗

  • Secondary technical reporting rather than a supplier process specification.

    Semiconductor Engineering, Current HBM known-good-stack test flows (opens the source) ↗

  • MR-MUF is supplier-specific.

    SK hynix, SK hynix MR-MUF heat-control history (opens the source) ↗

  • Forward-looking company technical analysis. Timing depends on cost, process maturity, equipment, generation, and supplier implementation.

    SK hynix, SK hynix hybrid-bonding technical note (opens the source) ↗

  • Paid/summary market estimates can change and are not company filings.

    TrendForce, HBM Industry Analysis, Q2 2026 (opens the source) ↗

  • Customer identities, volumes, pricing, cancellation terms, and final deployments are not disclosed. Performance/yield leadership language is promotional.

    SK hynix, SK hynix Q2 2026 results (opens the source) ↗

  • Vendor comparison to its own prior ramp. Revenue is not units, market share, customer deployment, or industry revenue.

    Micron, Micron fiscal Q3 2026 prepared remarks (opens the source) ↗

  • Proves contracted allocation for Micron only, not industry-wide physical shipment or universal unavailability.

    Micron, Micron fiscal Q1 2026 presentation (opens the source) ↗

  • The undersupply statement covers the broader memory market and product mix; it does not prove every HBM product or customer is equally constrained.

    Samsung Electronics, Samsung Q2 2026 results (opens the source) ↗

  • Announcement and construction milestone, not present operating capacity or guaranteed schedule. Scope/figure may have evolved from the 2024 plan.

    SK hynix, SK hynix Indiana groundbreaking (opens the source) ↗

  • The award record is not evidence that all funds have been disbursed or that the facility is operating.

    US National Institute of Standards and Technology, Current NIST CHIPS award listing for SK hynix Indiana (opens the source) ↗

  • Government assessment at the date; milestone-based award and planned facility, not operating output.

    US Department of Commerce, US CHIPS award for SK hynix HBM packaging (opens the source) ↗

  • Regulatory scope depends on technical thresholds, destination, end use, and current rules.

    US Bureau of Industry and Security / Federal Register, US advanced HBM export controls (opens the source) ↗

  • Classification, destination, end user, packaging site, technical parameters, and other EAR provisions can change the result. The documentary is not legal advice.

    US Bureau of Industry and Security, Current BIS License Exception HBM rule (opens the source) ↗

  • Reported speedups are tied to the paper's models, sequence lengths, software, and hardware.

    NeurIPS, FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness (opens the source) ↗

Our conclusion from the sources

The finished accelerator package, rather than the compute die alone, is becoming a meaningful unit of system competition.

Sources, by chapter

“This is an extraordinarily advanced computing package.”

As checked: HBM is vertically stacked DRAM connected through a very wide interface and placed in the same package as a host accelerator.

  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)
  • Company↗AMD launches first commercial HBM GPU familyAMD · 16 Jun 2015 (opens the source)
  • Company↗SK hynix HBM development historySK hynix · 2022 (opens the source)

“NVIDIA says one Rubin GPU can carry up to 288 gigabytes of HBM4 and move data at more than 19 terabytes per second.”

As checked: NVIDIA specifies up to 288 GB of HBM4 per Rubin GPU; current official pages list either 19.2 or up to 22 TB/s of bandwidth depending on the page/configuration.

  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)

“That is a river of information. And the processor can still end up waiting.”

As checked: Without speculative decoding, token-by-token LLM decode is commonly memory-bandwidth-bound, while prompt prefill commonly produces larger compute-bound matrix operations.

  • Research↗Co-Designing AI Model Attention for Fast, Interactive Long-Context InferenceNVIDIA Developer · 2026 (opens the source)

Our conclusion from the sources

“So the AI chip race has produced another race, hidden inside the same package.”

As checked: The finished accelerator package, rather than the compute die alone, is becoming a meaningful unit of system competition.

  • Filing↗TSMC 2025 Annual ReportTSMC · 2026 (opens the source)
  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)

Also used in this chapter

  • Research↗Roofline performance modelLawrence Berkeley National Laboratory · (opens the source)

“Imagine a restaurant with hundreds of chefs and one narrow ingredient door.”

As checked: A workload can be limited by compute throughput or memory bandwidth depending on how much arithmetic it performs per byte moved.

  • Research↗Roofline performance modelLawrence Berkeley National Laboratory · (opens the source)

Also used in this chapter

  • Research↗Co-Designing AI Model Attention for Fast, Interactive Long-Context InferenceNVIDIA Developer · 2026 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)
  • Company↗AMD launches first commercial HBM GPU familyAMD · 16 Jun 2015 (opens the source)
  • Company↗SK hynix HBM development historySK hynix · 2022 (opens the source)

“HBM4 doubles the interface cited for HBM3E, from 1,024 to 2,048 data connections per stack. Samsung says its fastest HBM4 configuration can reach up to 3.3 terabytes per second for one stack.”

As checked: HBM4 doubles the cited per-stack data interface from 1,024 to 2,048 I/Os relative to HBM3E.

  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)

“HBM4 doubles the interface cited for HBM3E, from 1,024 to 2,048 data connections per stack. Samsung says its fastest HBM4 configuration can reach up to 3.3 terabytes per second for one stack.”

As checked: Samsung began HBM4 mass production and commercial shipment in February 2026, offering 12-layer 24-36 GB products and reporting up to 3.3 TB/s per stack.

  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)

“And none of this began with generative AI. AMD and SK hynix brought HBM to commercial graphics cards in 2015, when the hungry machine was a gaming GPU.”

As checked: HBM existed before the generative-AI boom; AMD commercialized the first HBM-powered GPU family in 2015 after development with SK hynix.

  • Company↗AMD launches first commercial HBM GPU familyAMD · 16 Jun 2015 (opens the source)
  • Company↗SK hynix HBM development historySK hynix · 2022 (opens the source)

“But proximity alone is not enough. Thousands of lanes need somewhere to run.”

As checked: TSMC CoWoS integrates logic SoCs and HBM stacks, making advanced packaging part of accelerator capability rather than a cosmetic final step.

  • Filing↗TSMC 2025 Annual ReportTSMC · 2026 (opens the source)

Also used in this chapter

  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)
  • Company↗NVIDIA HGX H100/H200/B200 component specificationsNVIDIA documentation · current at 18 Oct 2026 (opens the source)

“And HBM4 makes the relationships even tighter. Its base die uses advanced logic, so memory design now reaches into the foundry and packaging worlds.”

As checked: HBM4 makes compute-memory co-design more important by using advanced logic base dies and a wider interface.

  • Research↗Co-Designing AI Model Attention for Fast, Interactive Long-Context InferenceNVIDIA Developer · 2026 (opens the source)
  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)

“SK hynix works with TSMC on its HBM4 base die and CoWoS integration. Samsung describes a more integrated route, combining its memory, foundry, and packaging capabilities around a four-nanometer base die.”

As checked: SK hynix uses TSMC advanced logic for its HBM4 base die and collaborates with TSMC on CoWoS integration.

  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)

“Designing that machine is hard.”

As checked: Stacking multiple TSV-connected dies creates distinct yield, test, and reliability challenges.

  • Research↗TSV built-in self-repair for HBM yield and reliabilityIEEE Transactions on VLSI Systems · 2023 (opens the source)
  • Research↗SK hynix TSV wafer-level packaging processSK hynix · 2023 (opens the source)
  • Research↗Advantest HBM test-flow briefingAdvantest · 29 Nov 2023 (opens the source)
  • Research↗Current HBM known-good-stack test flowsSemiconductor Engineering · 12 May 2026 (opens the source)

Also used in this chapter

  • Filing↗TSMC 2025 Annual ReportTSMC · 2026 (opens the source)
  • Company↗AMD launches first commercial HBM GPU familyAMD · 16 Jun 2015 (opens the source)
  • Company↗SK hynix HBM development historySK hynix · 2022 (opens the source)

“The testing cannot happen only at the end.”

As checked: HBM manufacturing relies on screening before stacking and repeated testing after stacking because assembly can introduce connection, stress, and yield failures even when constituent dies passed earlier tests.

  • Research↗TSV built-in self-repair for HBM yield and reliabilityIEEE Transactions on VLSI Systems · 2023 (opens the source)
  • Research↗SK hynix TSV wafer-level packaging processSK hynix · 2023 (opens the source)
  • Research↗Advantest HBM test-flow briefingAdvantest · 29 Nov 2023 (opens the source)
  • Research↗Current HBM known-good-stack test flowsSemiconductor Engineering · 12 May 2026 (opens the source)

Also used in this chapter

  • Company filing↗Micron HBM wafer-intensity presentationMicron · 2024 (opens the source)

“Now make each floor communicate faster.”

As checked: Higher stack density and faster interfaces make heat removal and thermal resistance important HBM design constraints.

  • Research↗SK hynix MR-MUF heat-control historySK hynix · 2024 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)

“Future stacks may use hybrid bonding, joining copper connections more directly and reducing space occupied by microscopic bumps. But adoption depends on cost, process maturity, and the generation being built.”

As checked: Future HBM stacks may use hybrid bonding to connect copper more directly and reduce space and resistance associated with micro-bumps, but adoption is not yet universal.

  • Research↗SK hynix hybrid-bonding technical noteSK hynix · 25 Aug 2026 (opens the source)

Also used in this chapter

  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)
  • Research↗Co-Designing AI Model Attention for Fast, Interactive Long-Context InferenceNVIDIA Developer · 2026 (opens the source)
  • Research↗TSV built-in self-repair for HBM yield and reliabilityIEEE Transactions on VLSI Systems · 2023 (opens the source)
  • Research↗SK hynix TSV wafer-level packaging processSK hynix · 2023 (opens the source)
  • Research↗Advantest HBM test-flow briefingAdvantest · 29 Nov 2023 (opens the source)
  • Research↗Current HBM known-good-stack test flowsSemiconductor Engineering · 12 May 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)

“By 2026, the established HBM market was dominated by three companies: SK hynix, Samsung, and Micron.”

As checked: SK hynix, Samsung, and Micron are the three major established HBM suppliers at the 2026 checkpoint.

  • Research↗HBM Industry Analysis, Q2 2026TrendForce · 2026 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix Q2 2026 resultsSK hynix · 29 Jul 2026 (opens the source)
  • Company↗Micron HBM4 high-volume production announcementMicron · 2026 (opens the source)
  • Company↗Micron fiscal Q3 2026 prepared remarksMicron · fiscal Q3 2026 (opens the source)
  • Company↗Micron fiscal Q1 2026 presentationMicron · fiscal Q1 2026 (opens the source)

“SK hynix pairs its memory and stacking expertise with TSMC's advanced logic and packaging ecosystem. The company said it began mass shipments of HBM4 in the second quarter of 2026 and planned a second-half ramp.”

As checked: SK hynix began mass shipments of HBM4 in Q2 2026 and planned to ramp production in H2.

  • Company↗SK hynix Q2 2026 resultsSK hynix · 29 Jul 2026 (opens the source)

“Micron, the US-headquartered supplier, said HBM4 volume shipments began in the first quarter. By its fiscal third quarter, it said it had shipped more than one billion dollars in HBM4 revenue.”

As checked: Micron reported HBM4 volume shipments beginning in Q1 2026 and more than $1 billion in HBM4 revenue shipped by fiscal Q3 2026.

  • Company↗Micron HBM4 high-volume production announcementMicron · 2026 (opens the source)
  • Company↗Micron fiscal Q3 2026 prepared remarksMicron · fiscal Q3 2026 (opens the source)

Also used in this chapter

  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)

“Samsung forecast that the broader memory market would remain undersupplied in the second half of 2026 despite production increases. Broader memory - not proof that every Samsung HBM product was unavailable.”

As checked: Samsung expected memory supply constraints to continue in H2 2026 despite production increases.

  • Company↗Samsung Q2 2026 resultsSamsung Electronics · 30 Jul 2026 (opens the source)

“But adding new capacity years ahead is nothing like restocking an empty warehouse.”

As checked: New HBM/advanced-packaging capacity takes years to construct; SK hynix's 2026 Indiana groundbreaking targets mass production in H2 2029.

  • Government↗Current NIST CHIPS award listing for SK hynix IndianaUS National Institute of Standards and Technology · checked 20 Oct 2026 (opens the source)
  • Company↗SK hynix Indiana groundbreakingSK hynix · 28 Aug 2026 (opens the source)

Also used in this chapter

  • Company filing↗Micron HBM wafer-intensity presentationMicron · 2024 (opens the source)

“In August 2026, SK hynix broke ground on an Indiana HBM packaging and research facility.”

As checked: The United States is supporting domestic HBM advanced-packaging capacity through the SK hynix Indiana project.

  • Government↗US CHIPS award for SK hynix HBM packagingUS Department of Commerce · 19 Dec 2024 (opens the source)
  • Government↗Current NIST CHIPS award listing for SK hynix IndianaUS National Institute of Standards and Technology · checked 20 Oct 2026 (opens the source)
  • Company↗SK hynix Indiana groundbreakingSK hynix · 28 Aug 2026 (opens the source)

“The United States controls certain advanced HBM in defined export contexts. It is not a universal HBM ban; classification, destination, customer, and packaging arrangements matter.”

As checked: Advanced HBM is strategically controlled by the United States because it is a key component of advanced AI and supercomputing systems.

  • Regulator↗US advanced HBM export controlsUS Bureau of Industry and Security / Federal Register · 2 Dec 2024 onward (opens the source)
  • Regulator↗Current BIS License Exception HBM ruleUS Bureau of Industry and Security · checked 20 Oct 2026 (opens the source)

“But spending billions to move more data is only half the answer.”

As checked: Software can materially reduce HBM traffic; FlashAttention reorganizes exact attention to reduce reads/writes between HBM and on-chip SRAM.

  • Research↗FlashAttention: Fast and Memory-Efficient Exact Attention with IO-AwarenessNeurIPS · 2022 (opens the source)

This chapter states no new facts of its own.

Also used in this chapter

  • Filing↗TSMC 2025 Annual ReportTSMC · 2026 (opens the source)
  • Research↗NVIDIA Rubin architecture and current specification pagesNVIDIA · 21 Jul 2026 and current pages checked 20 Oct 2026 (opens the source)
  • Research↗Co-Designing AI Model Attention for Fast, Interactive Long-Context InferenceNVIDIA Developer · 2026 (opens the source)
  • Research↗FlashAttention: Fast and Memory-Efficient Exact Attention with IO-AwarenessNeurIPS · 2022 (opens the source)
  • Company↗Samsung commercial HBM4 shipmentsSamsung Electronics · 12 Feb 2026 (opens the source)
  • Company↗SK hynix partnership with TSMCSK hynix · 19 Apr 2024 (opens the source)
  • Company↗AMD launches first commercial HBM GPU familyAMD · 16 Jun 2015 (opens the source)
  • Company↗SK hynix HBM development historySK hynix · 2022 (opens the source)

What you are seeing

Every scene of the film is one of four kinds, and the picture always says which.

  • evidence

    Real evidence

    A documented fact, attributed and dated: a regulator, a record or a company says.

  • illustrated

    Reconstruction

    A real case redrawn in our style: no logos, no real buildings.

  • explanation

    Explanation

    The idea itself, drawn with our own pictures.

  • scenario

    Scenario

    A possible future: always labelled, never shown as fact.

Real evidence · 17

  • HBM4 doubles the interface cited for HBM3E, from 1,024 to…
  • SK hynix works with TSMC on its HBM4 base die…
  • The capacity cost is substantial too. Micron estimated that, for…
  • SK hynix uses advanced MR-MUF, connecting multiple dies and filling…
  • By 2026, the established HBM market was dominated by three…
  • SK hynix pairs its memory and stacking expertise with TSMC's…
  • Samsung takes a more vertically integrated route. It combines memory…
  • Micron, the US-headquartered supplier, said HBM4 volume shipments began in…
  • In December 2025, Micron said price-and-volume agreements covered its entire…
  • SK hynix said it had long-term agreements with around ten…
  • Samsung forecast that the broader memory market would remain undersupplied…
  • In August 2026, SK hynix broke ground on an Indiana…
  • The company describes the expected investment as more than four…
  • The memory wafers are expected to arrive from Korea. Indiana…
  • SK hynix said more than one hundred companies were being…
  • The federal award described an approximately 3.87-billion-dollar project and up…
  • The United States controls certain advanced HBM in defined export…

Reconstruction · 1

  • And none of this began with generative AI. AMD and…

Explanation · 71

  • This is an extraordinarily advanced computing package.
  • At its center sits the celebrity: an AI processor built…
  • But look beside it.
  • Those blocks surrounding the processor are not supporting actors. They…
  • NVIDIA says one Rubin GPU can carry up to 288…
  • That is a river of information. And the processor can…
  • Because calculations require ingredients: model weights, activations, and the growing…
  • If those bytes arrive too slowly, expensive arithmetic machinery sits…
  • So the AI chip race has produced another race, hidden…
  • Engineers did not merely make memory faster. They sliced it…
  • That door has three problems people casually call speed.
  • Capacity is how many ingredients fit in the pantry. Latency…
  • Processors face the same arithmetic. A task doing lots of…
  • During inference, the initial prompt often creates large operations that…
  • Commonly - not always.
  • Batching, caching, speculative decoding, model architecture, networking, and software can…
  • But when the ingredient door is the problem, one solution…
  • Ordinary memory can sit farther away, reached through narrower connections…
  • HBM solves a different problem.
  • Start with thin slices of DRAM: the silicon that stores…
  • Then etch microscopic channels through the silicon and fill them…
  • Stacking creates substantial capacity in a small footprint. More importantly,…
  • Today, several towers sit beside advanced accelerator logic inside one…
  • But proximity alone is not enough. Thousands of lanes need…
  • Beneath the processor and memory towers lies a piece most…
  • Think of it as a city grid. The processor and…
  • This is called 2.5D integration. The memory is stacked in…
  • TSMC's CoWoS is one way to build this kind of…
  • And HBM4 makes the relationships even tighter. Its base die…
  • Neither arrangement is automatically superior. Both reveal the same change.
  • The product is no longer one rectangle of compute. It…
  • Designing that machine is hard.
  • The animation says: take good memory chips and stack them.
  • Fabricate the DRAM and base dies. Prepare their vertical connections.…
  • That is the broad journey, not one universal recipe. Manufacturers…
  • The testing cannot happen only at the end.
  • A failed die buried inside a tall, expensive stack wastes…
  • Even that name is optimistic. A layer can pass alone…
  • Not three times the price. Not every HBM generation forever.
  • Three times the starting silicon for that comparison - before…
  • Now make each floor communicate faster.
  • More electrical activity produces heat. More layers make the escape…
  • The structure is fragile.
  • Each layer is thin silicon. Between layers sit thousands of…
  • So the material between the dies is not merely glue.…
  • Those approaches are supplier-specific, not one industry recipe.
  • The challenge is a balancing act. Increase bandwidth without wasting…
  • The memory race is several races tied together.
  • That does not mean a fourth company can never enter.…
  • These announcements are company reports, not an independent podium ranking.…
  • The competition is less photogenic: qualify with customers, control heat,…
  • Which creates a strange market.
  • Customers reserve tomorrow's memory before tomorrow's computers exist.
  • That did not mean every stack was manufactured, shipped, or…
  • The distinction matters because an HBM order is a chain…
  • Customers need DRAM wafers, stacking and testing capacity, advanced logic…
  • So `sold out` is the tempting headline, but `allocated in…
  • It means equipment, cleanrooms, trained workers, partner companies - and…
  • Roughly three years after groundbreaking.
  • Tiny towers have become industrial policy.
  • But spending billions to move more data is only half…
  • Return to the package.
  • HBM gives the processor a nearby pantry and a wide…
  • But engineers can change the recipe.
  • FlashAttention reorganizes exact attention calculations so the processor makes fewer…
  • And the bottleneck moves.
  • If data arrives faster, arithmetic may become the limit. As…
  • No villain permanently holds back all AI.
  • The towers reveal how the entire machine is changing. The…
  • The future of AI hardware will not be won by…
  • It will be won by moving the right bytes to…

Scenario · 5

  • Imagine a restaurant with hundreds of chefs and one narrow…
  • Adding chefs will not help if they spend dinner waiting…
  • The factory hears more.
  • Future stacks may use hybrid bonding, joining copper connections more…
  • But adding new capacity years ahead is nothing like restocking…

Transcript

0 · The chip beside the chip

  • This is an extraordinarily advanced computing package.
  • At its center sits the celebrity: an AI processor built for absurd amounts of calculation.
  • But look beside it.
  • Those blocks surrounding the processor are not supporting actors. They are towers of memory, inside the same package because distance has become the enemy.
  • NVIDIA says one Rubin GPU can carry up to 288 gigabytes of HBM4 and move data at more than 19 terabytes per second.
  • That is a river of information. And the processor can still end up waiting.
  • Because calculations require ingredients: model weights, activations, and the growing record of what has already been said.
  • If those bytes arrive too slowly, expensive arithmetic machinery sits hungry.
  • So the AI chip race has produced another race, hidden inside the same package.
  • Engineers did not merely make memory faster. They sliced it thin, punched connections through it, stacked it into towers, and built an industrial system around feeding the chip beside the chip.

1 · The wall between math and memory

  • Imagine a restaurant with hundreds of chefs and one narrow ingredient door.
  • Adding chefs will not help if they spend dinner waiting for tomatoes.
  • That door has three problems people casually call speed.
  • Capacity is how many ingredients fit in the pantry. Latency is how long one delivery takes. Bandwidth is how much can pass through the door every second.
  • Processors face the same arithmetic. A task doing lots of calculation with each byte is limited by compute. A task repeatedly fetching enormous amounts of data may be limited by memory bandwidth.
  • During inference, the initial prompt often creates large operations that keep the processor busy. But generating tokens commonly requires rereading model weights and cached context, making bandwidth the tighter constraint.
  • Commonly - not always.
  • Batching, caching, speculative decoding, model architecture, networking, and software can move the limit. Different kitchens run out of different things.
  • But when the ingredient door is the problem, one solution is obvious: make it extraordinarily wide, then move the pantry right beside the chefs.

2 · The memory tower

  • Ordinary memory can sit farther away, reached through narrower connections across a circuit board. That remains useful because computers need many kinds of memory at different prices and capacities.
  • HBM solves a different problem.
  • Start with thin slices of DRAM: the silicon that stores data. Instead of spreading them across the board, place them vertically above a base die.
  • Then etch microscopic channels through the silicon and fill them with electrical connections. These are through-silicon vias, or TSVs - tiny elevators carrying signals between floors.
  • Stacking creates substantial capacity in a small footprint. More importantly, the completed tower can communicate through a vast number of connections at once.
  • HBM4 doubles the interface cited for HBM3E, from 1,024 to 2,048 data connections per stack. Samsung says its fastest HBM4 configuration can reach up to 3.3 terabytes per second for one stack.
  • And none of this began with generative AI. AMD and SK hynix brought HBM to commercial graphics cards in 2015, when the hungry machine was a gaming GPU.
  • Today, several towers sit beside advanced accelerator logic inside one package - beside it, not inside the processor itself.
  • But proximity alone is not enough. Thousands of lanes need somewhere to run.

3 · The package is the machine

  • Beneath the processor and memory towers lies a piece most people never see: a dense routing layer called an interposer.
  • Think of it as a city grid. The processor and HBM towers are separate buildings, placed side by side, while microscopic roads underneath connect them more densely than an ordinary circuit board could.
  • This is called 2.5D integration. The memory is stacked in three dimensions, but the completed towers and processor remain horizontal neighbors on a shared package.
  • TSMC's CoWoS is one way to build this kind of system. It is a proprietary packaging platform, not the generic name for every HBM package.
  • And HBM4 makes the relationships even tighter. Its base die uses advanced logic, so memory design now reaches into the foundry and packaging worlds.
  • SK hynix works with TSMC on its HBM4 base die and CoWoS integration. Samsung describes a more integrated route, combining its memory, foundry, and packaging capabilities around a four-nanometer base die.
  • Neither arrangement is automatically superior. Both reveal the same change.
  • The product is no longer one rectangle of compute. It is the processor, memory, base dies, interposer, packaging, power delivery, and software behaving as one machine.
  • Designing that machine is hard.

4 · Build a tower from working floors

  • The animation says: take good memory chips and stack them.
  • The factory hears more.
  • Fabricate the DRAM and base dies. Prepare their vertical connections. Screen them. Thin the delicate silicon. Form microscopic bumps, align the layers, bond them, protect the spaces between them, test the stack, then integrate it into a larger package and qualify everything again.
  • That is the broad journey, not one universal recipe. Manufacturers can form, thin, stack, bond, mold, and test at different points.
  • The testing cannot happen only at the end.
  • A failed die buried inside a tall, expensive stack wastes every working layer attached to it. So manufacturers screen for known-good dies before stacking, then test the known-good stack afterward.
  • Even that name is optimistic. A layer can pass alone while bonding introduces a bad connection, a TSV fails, or thin silicon bends under stress. Redundant paths and repair can rescue some faults, but not every assembly.
  • The capacity cost is substantial too. Micron estimated that, for equal bit output on the same process node, HBM3E consumed roughly three times the wafer supply of DDR5.
  • Not three times the price. Not every HBM generation forever.
  • Three times the starting silicon for that comparison - before the tower is finished.

5 · Heat has nowhere to go

  • Now make each floor communicate faster.
  • More electrical activity produces heat. More layers make the escape route longer. And the interior of a memory tower cannot touch the cooling plate above it.
  • The structure is fragile.
  • Each layer is thin silicon. Between layers sit thousands of connections and several materials that expand differently as temperatures change. Heat them, cool them, and the stack can warp, crack, or pull against its bonds.
  • So the material between the dies is not merely glue. Underfill protects the connections, distributes stress, and helps the stack survive manufacturing and operation.
  • SK hynix uses advanced MR-MUF, connecting multiple dies and filling the gaps with protective molding material. Samsung says its HBM4 improves thermal resistance and heat dissipation relative to its HBM3E.
  • Those approaches are supplier-specific, not one industry recipe.
  • Future stacks may use hybrid bonding, joining copper connections more directly and reducing space occupied by microscopic bumps. But adoption depends on cost, process maturity, and the generation being built.
  • The challenge is a balancing act. Increase bandwidth without wasting power. Add capacity without making the tower too tall. Remove heat without damaging yield.
  • The memory race is several races tied together.

6 · Three ways to build the same future

  • By 2026, the established HBM market was dominated by three companies: SK hynix, Samsung, and Micron.
  • That does not mean a fourth company can never enter. Producing these towers at commercial scale requires years of process knowledge.
  • SK hynix pairs its memory and stacking expertise with TSMC's advanced logic and packaging ecosystem. The company said it began mass shipments of HBM4 in the second quarter of 2026 and planned a second-half ramp.
  • Samsung takes a more vertically integrated route. It combines memory fabrication, a foundry, and advanced packaging within one corporate group. Samsung reported commercial HBM4 shipments beginning in February 2026.
  • Micron, the US-headquartered supplier, said HBM4 volume shipments began in the first quarter. By its fiscal third quarter, it said it had shipped more than one billion dollars in HBM4 revenue.
  • These announcements are company reports, not an independent podium ranking. Revenue is not market share, and shipping memory does not prove which customer systems are operating.
  • The competition is less photogenic: qualify with customers, control heat, improve repeatable yield, and deliver enormous quantities on schedule.
  • Which creates a strange market.
  • Customers reserve tomorrow's memory before tomorrow's computers exist.

7 · Sold before it exists

  • In December 2025, Micron said price-and-volume agreements covered its entire calendar-2026 HBM supply, including HBM4.
  • That did not mean every stack was manufactured, shipped, or installed. It meant customers had committed to future output before all of it existed.
  • SK hynix said it had long-term agreements with around ten customers and was discussing more. It did not publish their identities, prices, or volumes.
  • Samsung forecast that the broader memory market would remain undersupplied in the second half of 2026 despite production increases. Broader memory - not proof that every Samsung HBM product was unavailable.
  • The distinction matters because an HBM order is a chain of reservations.
  • Customers need DRAM wafers, stacking and testing capacity, advanced logic for base dies, and packaging slots that combine memory with processors. A delay in any one can hold up a more expensive system.
  • So `sold out` is the tempting headline, but `allocated in advance` is usually more honest.
  • But adding new capacity years ahead is nothing like restocking an empty warehouse.
  • It means equipment, cleanrooms, trained workers, partner companies - and another physical factory.

8 · A $4 billion bet on tiny towers

  • In August 2026, SK hynix broke ground on an Indiana HBM packaging and research facility.
  • The company describes the expected investment as more than four billion dollars. Its cleanroom is planned to open in October 2028, with next-generation HBM mass production targeted for the second half of 2029.
  • Roughly three years after groundbreaking.
  • The memory wafers are expected to arrive from Korea. Indiana will perform advanced packaging and testing with a Purdue research testbed.
  • SK hynix said more than one hundred companies were being considered as suppliers for materials, components, and equipment.
  • The federal award described an approximately 3.87-billion-dollar project and up to 458 million dollars in direct funding. Those are snapshots, not contradictory price tags.
  • The United States controls certain advanced HBM in defined export contexts. It is not a universal HBM ban; classification, destination, customer, and packaging arrangements matter.
  • Tiny towers have become industrial policy.
  • But spending billions to move more data is only half the answer.

9 · Feed the machine, then move the limit

  • Return to the package.
  • HBM gives the processor a nearby pantry and a wide door. That can transform workloads that move data repeatedly.
  • But engineers can change the recipe.
  • FlashAttention reorganizes exact attention calculations so the processor makes fewer trips between HBM and its smaller on-chip memory. It does not remove HBM. It avoids unnecessary traffic.
  • And the bottleneck moves.
  • If data arrives faster, arithmetic may become the limit. As accelerators work faster, communication among thousands may dominate. A model may run out of capacity. A rack may run into power or cooling. Software overhead may consume what the hardware gained.
  • No villain permanently holds back all AI.
  • The towers reveal how the entire machine is changing. The processor is no longer the whole product, if it ever was. Useful performance increasingly emerges from compute, memory, packaging, networks, power, cooling, and software designed together.
  • The future of AI hardware will not be won by performing the most calculations.
  • It will be won by moving the right bytes to the right place at the right time.

How this film was made

Researched, written, drawn and checked by our team. We use AI tools throughout: research, writing, code-drawn animation, narration and music. Every claim is linked to its source.

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