Films The memory towers behind the AI boom

Beside the fastest AI processors sit towers of stacked memory. This film opens one package to show why memory bandwidth matters, how the towers are built, tested and cooled, who makes them, and why their supply is reserved years before the computers exist.
HBM is vertically stacked DRAM connected through a very wide interface and placed in the same package as a host accelerator.
Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix partnership with TSMC (opens the source) ↗ · AMD: AMD launches first commercial HBM GPU family (opens the source) ↗ · SK hynix: SK hynix HBM development history (opens the source) ↗
NVIDIA specifies up to 288 GB of HBM4 per Rubin GPU; current official pages list either 19.2 or up to 22 TB/s of bandwidth depending on the page/configuration.
NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗
Without speculative decoding, token-by-token LLM decode is commonly memory-bandwidth-bound, while prompt prefill commonly produces larger compute-bound matrix operations.
First, yield, performance, efficiency, and thermal comparisons are company claims.
Samsung Electronics, Samsung commercial HBM4 shipments (opens the source) ↗
Agreement does not mean TSMC makes SK hynix DRAM core dies or that every HBM supplier uses the same structure.
SK hynix, SK hynix partnership with TSMC (opens the source) ↗
AMD's 2015 comparative marketing does not describe current HBM4 or AI performance.
AMD, AMD launches first commercial HBM GPU family (opens the source) ↗
A workload can be limited by compute throughput or memory bandwidth depending on how much arithmetic it performs per byte moved.
Lawrence Berkeley National Laboratory: Roofline performance model (opens the source) ↗
HBM4 doubles the cited per-stack data interface from 1,024 to 2,048 I/Os relative to HBM3E.
NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗
Samsung began HBM4 mass production and commercial shipment in February 2026, offering 12-layer 24-36 GB products and reporting up to 3.3 TB/s per stack.
as the company reports
Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗
HBM existed before the generative-AI boom; AMD commercialized the first HBM-powered GPU family in 2015 after development with SK hynix.
AMD: AMD launches first commercial HBM GPU family (opens the source) ↗ · SK hynix: SK hynix HBM development history (opens the source) ↗
TSMC CoWoS integrates logic SoCs and HBM stacks, making advanced packaging part of accelerator capability rather than a cosmetic final step.
HBM4 makes compute-memory co-design more important by using advanced logic base dies and a wider interface.
NVIDIA Developer: Co-Designing AI Model Attention for Fast, Interactive Long-Context Inference (opens the source) ↗ · NVIDIA: NVIDIA Rubin architecture and current specification pages (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix partnership with TSMC (opens the source) ↗
SK hynix uses TSMC advanced logic for its HBM4 base die and collaborates with TSMC on CoWoS integration.
SK hynix: SK hynix partnership with TSMC (opens the source) ↗
Stacking multiple TSV-connected dies creates distinct yield, test, and reliability challenges.
IEEE Transactions on VLSI Systems: TSV built-in self-repair for HBM yield and reliability (opens the source) ↗ · SK hynix: SK hynix TSV wafer-level packaging process (opens the source) ↗ · Advantest: Advantest HBM test-flow briefing (opens the source) ↗ · Semiconductor Engineering: Current HBM known-good-stack test flows (opens the source) ↗
HBM manufacturing relies on screening before stacking and repeated testing after stacking because assembly can introduce connection, stress, and yield failures even when constituent dies passed earlier tests.
IEEE Transactions on VLSI Systems: TSV built-in self-repair for HBM yield and reliability (opens the source) ↗ · SK hynix: SK hynix TSV wafer-level packaging process (opens the source) ↗ · Advantest: Advantest HBM test-flow briefing (opens the source) ↗ · Semiconductor Engineering: Current HBM known-good-stack test flows (opens the source) ↗
Higher stack density and faster interfaces make heat removal and thermal resistance important HBM design constraints.
SK hynix: SK hynix MR-MUF heat-control history (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗
Future HBM stacks may use hybrid bonding to connect copper more directly and reduce space and resistance associated with micro-bumps, but adoption is not yet universal.
SK hynix: SK hynix hybrid-bonding technical note (opens the source) ↗
SK hynix, Samsung, and Micron are the three major established HBM suppliers at the 2026 checkpoint.
TrendForce: HBM Industry Analysis, Q2 2026 (opens the source) ↗ · Samsung Electronics: Samsung commercial HBM4 shipments (opens the source) ↗ · SK hynix: SK hynix Q2 2026 results (opens the source) ↗ · Micron: Micron HBM4 high-volume production announcement (opens the source) ↗ · Micron: Micron fiscal Q3 2026 prepared remarks (opens the source) ↗ · Micron: Micron fiscal Q1 2026 presentation (opens the source) ↗
SK hynix began mass shipments of HBM4 in Q2 2026 and planned to ramp production in H2.
as the company reports
Micron reported HBM4 volume shipments beginning in Q1 2026 and more than $1 billion in HBM4 revenue shipped by fiscal Q3 2026.
as the company reports
Micron: Micron HBM4 high-volume production announcement (opens the source) ↗ · Micron: Micron fiscal Q3 2026 prepared remarks (opens the source) ↗
Samsung expected memory supply constraints to continue in H2 2026 despite production increases.
Samsung Electronics: Samsung Q2 2026 results (opens the source) ↗
New HBM/advanced-packaging capacity takes years to construct; SK hynix's 2026 Indiana groundbreaking targets mass production in H2 2029.
US National Institute of Standards and Technology: Current NIST CHIPS award listing for SK hynix Indiana (opens the source) ↗ · SK hynix: SK hynix Indiana groundbreaking (opens the source) ↗
The United States is supporting domestic HBM advanced-packaging capacity through the SK hynix Indiana project.
US Department of Commerce: US CHIPS award for SK hynix HBM packaging (opens the source) ↗ · US National Institute of Standards and Technology: Current NIST CHIPS award listing for SK hynix Indiana (opens the source) ↗ · SK hynix: SK hynix Indiana groundbreaking (opens the source) ↗
Advanced HBM is strategically controlled by the United States because it is a key component of advanced AI and supercomputing systems.
US Bureau of Industry and Security / Federal Register: US advanced HBM export controls (opens the source) ↗ · US Bureau of Industry and Security: Current BIS License Exception HBM rule (opens the source) ↗
Software can materially reduce HBM traffic; FlashAttention reorganizes exact attention to reduce reads/writes between HBM and on-chip SRAM.
Company history.
SK hynix, SK hynix HBM development history (opens the source) ↗
Official NVIDIA pages do not currently show one uniform bandwidth figure. These are vendor specifications, not measured application throughput.
NVIDIA, NVIDIA Rubin architecture and current specification pages (opens the source) ↗
The model is an analytical framework; it does not prove that a particular AI workload is memory-bound without workload/platform inputs.
Lawrence Berkeley National Laboratory, Roofline performance model (opens the source) ↗
NVIDIA platform/model analysis.
Does not establish that all CoWoS capacity serves HBM, NVIDIA, or one product.
Supports mechanism, not one current vendor's production yield or defect rate.
An educational description of SK hynix-related packaging methods, not one mandatory sequence for every supplier, HBM generation, or bonding flow.
SK hynix, SK hynix TSV wafer-level packaging process (opens the source) ↗
Test-equipment supplier material. It establishes categories and insertion points, not a universal vendor recipe or current supplier yield.
Advantest, Advantest HBM test-flow briefing (opens the source) ↗
Secondary technical reporting rather than a supplier process specification.
Semiconductor Engineering, Current HBM known-good-stack test flows (opens the source) ↗
MR-MUF is supplier-specific.
SK hynix, SK hynix MR-MUF heat-control history (opens the source) ↗
Forward-looking company technical analysis. Timing depends on cost, process maturity, equipment, generation, and supplier implementation.
SK hynix, SK hynix hybrid-bonding technical note (opens the source) ↗
Paid/summary market estimates can change and are not company filings.
TrendForce, HBM Industry Analysis, Q2 2026 (opens the source) ↗
Customer identities, volumes, pricing, cancellation terms, and final deployments are not disclosed. Performance/yield leadership language is promotional.
Vendor comparison to its own prior ramp. Revenue is not units, market share, customer deployment, or industry revenue.
Micron, Micron fiscal Q3 2026 prepared remarks (opens the source) ↗
Proves contracted allocation for Micron only, not industry-wide physical shipment or universal unavailability.
Micron, Micron fiscal Q1 2026 presentation (opens the source) ↗
The undersupply statement covers the broader memory market and product mix; it does not prove every HBM product or customer is equally constrained.
Samsung Electronics, Samsung Q2 2026 results (opens the source) ↗
Announcement and construction milestone, not present operating capacity or guaranteed schedule. Scope/figure may have evolved from the 2024 plan.
SK hynix, SK hynix Indiana groundbreaking (opens the source) ↗
The award record is not evidence that all funds have been disbursed or that the facility is operating.
Government assessment at the date; milestone-based award and planned facility, not operating output.
US Department of Commerce, US CHIPS award for SK hynix HBM packaging (opens the source) ↗
Regulatory scope depends on technical thresholds, destination, end use, and current rules.
Classification, destination, end user, packaging site, technical parameters, and other EAR provisions can change the result. The documentary is not legal advice.
US Bureau of Industry and Security, Current BIS License Exception HBM rule (opens the source) ↗
Reported speedups are tied to the paper's models, sequence lengths, software, and hardware.
Our conclusion from the sources
The finished accelerator package, rather than the compute die alone, is becoming a meaningful unit of system competition.
“This is an extraordinarily advanced computing package.”
As checked: HBM is vertically stacked DRAM connected through a very wide interface and placed in the same package as a host accelerator.
“NVIDIA says one Rubin GPU can carry up to 288 gigabytes of HBM4 and move data at more than 19 terabytes per second.”
As checked: NVIDIA specifies up to 288 GB of HBM4 per Rubin GPU; current official pages list either 19.2 or up to 22 TB/s of bandwidth depending on the page/configuration.
“That is a river of information. And the processor can still end up waiting.”
As checked: Without speculative decoding, token-by-token LLM decode is commonly memory-bandwidth-bound, while prompt prefill commonly produces larger compute-bound matrix operations.
Our conclusion from the sources
“So the AI chip race has produced another race, hidden inside the same package.”
As checked: The finished accelerator package, rather than the compute die alone, is becoming a meaningful unit of system competition.
Also used in this chapter
“Imagine a restaurant with hundreds of chefs and one narrow ingredient door.”
As checked: A workload can be limited by compute throughput or memory bandwidth depending on how much arithmetic it performs per byte moved.
Also used in this chapter
“HBM4 doubles the interface cited for HBM3E, from 1,024 to 2,048 data connections per stack. Samsung says its fastest HBM4 configuration can reach up to 3.3 terabytes per second for one stack.”
As checked: HBM4 doubles the cited per-stack data interface from 1,024 to 2,048 I/Os relative to HBM3E.
“HBM4 doubles the interface cited for HBM3E, from 1,024 to 2,048 data connections per stack. Samsung says its fastest HBM4 configuration can reach up to 3.3 terabytes per second for one stack.”
As checked: Samsung began HBM4 mass production and commercial shipment in February 2026, offering 12-layer 24-36 GB products and reporting up to 3.3 TB/s per stack.
“And none of this began with generative AI. AMD and SK hynix brought HBM to commercial graphics cards in 2015, when the hungry machine was a gaming GPU.”
As checked: HBM existed before the generative-AI boom; AMD commercialized the first HBM-powered GPU family in 2015 after development with SK hynix.
“But proximity alone is not enough. Thousands of lanes need somewhere to run.”
As checked: TSMC CoWoS integrates logic SoCs and HBM stacks, making advanced packaging part of accelerator capability rather than a cosmetic final step.
Also used in this chapter
“And HBM4 makes the relationships even tighter. Its base die uses advanced logic, so memory design now reaches into the foundry and packaging worlds.”
As checked: HBM4 makes compute-memory co-design more important by using advanced logic base dies and a wider interface.
“SK hynix works with TSMC on its HBM4 base die and CoWoS integration. Samsung describes a more integrated route, combining its memory, foundry, and packaging capabilities around a four-nanometer base die.”
As checked: SK hynix uses TSMC advanced logic for its HBM4 base die and collaborates with TSMC on CoWoS integration.
“Designing that machine is hard.”
As checked: Stacking multiple TSV-connected dies creates distinct yield, test, and reliability challenges.
Also used in this chapter
“The testing cannot happen only at the end.”
As checked: HBM manufacturing relies on screening before stacking and repeated testing after stacking because assembly can introduce connection, stress, and yield failures even when constituent dies passed earlier tests.
Also used in this chapter
“Now make each floor communicate faster.”
As checked: Higher stack density and faster interfaces make heat removal and thermal resistance important HBM design constraints.
“Future stacks may use hybrid bonding, joining copper connections more directly and reducing space occupied by microscopic bumps. But adoption depends on cost, process maturity, and the generation being built.”
As checked: Future HBM stacks may use hybrid bonding to connect copper more directly and reduce space and resistance associated with micro-bumps, but adoption is not yet universal.
Also used in this chapter
“By 2026, the established HBM market was dominated by three companies: SK hynix, Samsung, and Micron.”
As checked: SK hynix, Samsung, and Micron are the three major established HBM suppliers at the 2026 checkpoint.
“SK hynix pairs its memory and stacking expertise with TSMC's advanced logic and packaging ecosystem. The company said it began mass shipments of HBM4 in the second quarter of 2026 and planned a second-half ramp.”
As checked: SK hynix began mass shipments of HBM4 in Q2 2026 and planned to ramp production in H2.
“Micron, the US-headquartered supplier, said HBM4 volume shipments began in the first quarter. By its fiscal third quarter, it said it had shipped more than one billion dollars in HBM4 revenue.”
As checked: Micron reported HBM4 volume shipments beginning in Q1 2026 and more than $1 billion in HBM4 revenue shipped by fiscal Q3 2026.
Also used in this chapter
“Samsung forecast that the broader memory market would remain undersupplied in the second half of 2026 despite production increases. Broader memory - not proof that every Samsung HBM product was unavailable.”
As checked: Samsung expected memory supply constraints to continue in H2 2026 despite production increases.
“But adding new capacity years ahead is nothing like restocking an empty warehouse.”
As checked: New HBM/advanced-packaging capacity takes years to construct; SK hynix's 2026 Indiana groundbreaking targets mass production in H2 2029.
Also used in this chapter
“In August 2026, SK hynix broke ground on an Indiana HBM packaging and research facility.”
As checked: The United States is supporting domestic HBM advanced-packaging capacity through the SK hynix Indiana project.
“The United States controls certain advanced HBM in defined export contexts. It is not a universal HBM ban; classification, destination, customer, and packaging arrangements matter.”
As checked: Advanced HBM is strategically controlled by the United States because it is a key component of advanced AI and supercomputing systems.
“But spending billions to move more data is only half the answer.”
As checked: Software can materially reduce HBM traffic; FlashAttention reorganizes exact attention to reduce reads/writes between HBM and on-chip SRAM.
This chapter states no new facts of its own.
Also used in this chapter
Every scene of the film is one of four kinds, and the picture always says which.
A documented fact, attributed and dated: a regulator, a record or a company says.
A real case redrawn in our style: no logos, no real buildings.
The idea itself, drawn with our own pictures.
A possible future: always labelled, never shown as fact.
Researched, written, drawn and checked by our team. We use AI tools throughout: research, writing, code-drawn animation, narration and music. Every claim is linked to its source.
No corrections to date.
Spotted an error? Write to [email protected] with the film's title.Spotted an error? Email us ↗